1. Field of the Invention
The present invention relates to telecommunications. More particularly, the present invention relates to the passing of high speed Asynchronous Transfer Mode (ATM) data or packet data over a standardized Universal Test and Operations Physical Interface for ATM (UTOPIA) bus.
2. State of the Art
Perhaps the most awaited, and now fastest growing technology in the field of telecommunications in the 1990's is known as ATM technology. ATM is providing a mechanism for removing performance limitations of local area networks (LANs) and wide area networks (WANs) and providing data transfers at a speed of on the order of gigabits/second. Within the ATM technology, a commonly used interface specification between chips on a board for passing ATM cells is the UTOPIA (Universal Test & Operations PHY Interface for ATM) interface. The UTOPIA interface is specified in ATM Forum standard specifications, including: af-phy-0017.000 (UTOPIA Level 1, Version 2.01 Mar. 21, 1994); af_phy—0039.000 (UTOPIA Level 2, Version 1, June 1995); and af-phy-00136.000 (UTOPIA 3 Physical Layer Interface November 1999) which are hereby incorporated by reference herein in their entireties. A typical application of the UTOPIA interface is supporting the connection between an ATM network processor and various PHY devices such as a DSL chip set and/or a SONET framer. UTOPIA is also used as the interface between a switch fabric and an ATM network processor.
UTOPIA supports three operation modes: single PHY operation mode, Multiple PHY (MPHY) with Direct Status Indication operation mode and MPHY with Multiplexed Status Polling operation mode. In the single PHY mode, the UTOPIA interface includes a data bus and a control bus. The operation of UTOPIA in the single PHY mode is relatively simple and straightforward. In MPHY operation mode, the UTOPIA interface includes a data bus, a control bus and an address bus. MPHY with Multiplexed Status Polling is used in most applications.
The MPHY UTOPIA transmit interface includes the following signals: transmit data (TxData), transmit address (TxAddr) and transmit control signals transmit cell available (TxClav), transmit enable (TxEnb*) and transmit start of cell (TxSOC). The receive interface includes the following signals: receive data (RxData), receive address (RxAddr) and receive control signals receive cell available (RxClav), receive enable (RxEnb*) and receive start of cell (RxSOC). A MPHY device may consist of multiple PHY ports, each PHY port having a one-to-one correspondence with a PHY Port address that is related to a UTOPIA address and Clav (Cell buffer available) signal.
Prior art FIG. 1 illustrates an example of a UTOPIA Level 2 interface supporting MPHY with Multiplexed Status Polling operation. As shown in FIG. 1, a transmit clock signal (TxClk) is used to clock control signals and data signals in the transmit direction (from the ATM device to the PHY devices). The TxData[15:0] signal is a 16-bit UTOPIA transmit data bus. The assertion of TxEnb* is coincident with the start of the cell transfer. TxSOC is used to indicate the start of cell position. TxClav is used to indicate that the PHY layer device is ready to receive a cell from the ATM layer device. TxAddr[4:0] is the UTOPIA address and is used to poll and select the appropriate MPHY device.
At the UTOPIA transmit interface, the ATM layer device polls the TxClav status of a PHY layer device by placing a specified address on the TxAddr bus for one clock cycle. The PHY layer device which is associated with the address on the TxAddr bus drives TxClav high (or low) during the next clock cycle during which the ATM device places a null address (1F) on the TxAddr bus. The ATM layer device checks TxClav at a certain time after it issues TxAddr. Based on polled TxClav information, the ATM layer device can select a PHY device and transfer data to this PHY device by driving TxEnb* and TxSOC signals.
Similarly, RxClk is the receive clock signal that is used to clock control signals and data in the receive direction (from the PHY device to the ATM device). RxData[15:0] is a 16-bit UTOPIA Receive bus. The assertion of RxEnb* is coincident with the start of the cell transfer. RxSOC is used to indicate the start of cell position. RxClav is used to indicate that the PHY layer device is ready to Receive a cell from the ATM layer device. RxAddr[4:0] is the UTOPIA address of the PHY device and is used by the ATM device to poll and select the appropriate PHY device in the receive direction.
At the UTOPIA receive interface, the ATM layer device polls the RxClav status of a PHY layer device by placing a specified address on RxAddr bus for one clock cycle. The PHY layer device which is associated with the address on the RxAddr bus drives RxClav high (or low) during the next clock cycle during which the ATM device places a null address (1F) on the RxAddr bus. The ATM layer device checks RxClav at a certain time after it issues RxAddr. Based on polled RxClav information, the ATM layer device can select a PHY device and receive data from this PHY device by driving the RxEnb* signal.
Certain timing requirements must be met for the Multiplexed Status Polling operation of the UTOPIA interface so that the ATM layer device can correctly detect Clav (Cell buffer available) information. FIG. 2 depicts the timing requirement for UTOPIA level 2 address polling. An ATM device starts driving UTOPIA address N at time t1. The PHY device having address N responds to address polling by driving the Clav signal high (or low) at time t2. The Clav becomes valid for the ATM device at time t3 (after transmission delay) as illustrated by the last line of the timing diagram. The ATM device checks the Clav signal at time t4 in order to accommodate a certain amount of transmission delay. To guarantee correct operation, the Clav signal must be valid before it is checked by ATM device, i.e. at some t3<t4. This is a necessary timing requirement for the UTOPIA interface.
This timing requirement of the UTOPIA interface is not difficult to meet if the ATM device and the PHY device are on the same circuit board. However, if the devices are even just a few feet apart, the timing requirement will not be met because the Clav signal will not arrive at the ATM device until some time after t4 and thus will not be recognized.
PCT International Publication Number WO 00/22784 describes a modified UTOPIA interface for inter-board applications where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. Output and input circuitry is provided in conjunction with the polling master and user ATM boards to accommodate hot insertion and to help drive the circuit. The master preferably includes an outgoing address latch and address latch control associated with the address bus and a register associated with the enable signal. The master also includes a hot insertion buffer on the incoming cell available (Clav) signal. The user device(s) include hot insertion buffers on the address bus, the data bus, and the enable signal. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot insertable UTOPIA interface is established.
Although the modified UTOPIA interface enables the creation of a proprietary backplane application, it is no longer a standard UTOPIA interface and cannot directly interface with standard devices having a standard UTOPIA interface.
The standard UTOPIA interface is used to support ATM cell transmission. In industry, the UTOPIA interface is also used to support packet transmission by adding some control signals such as SOP(Start Of Packet) and EOP(End Of Packet), etc. UTOPIA 2P developed by TranSwitch Corporation and POS-PHY developed by PMC-Sierra Inc. are two typical UTOPIA packet interfaces that have been popularly used in packet switching.
In the transmit direction, the UTOPIA packet interface defines an “Available Signal” which is similar to TxClav in the standard UTOPIA interface to indicate whether the PHY layer device has a certain buffer space called a Chunk (chunk size can be 16, 48, 64 bytes etc.) available to receive data. The UTOPIA packet interface also provides a control handshaking to halt data transfer once the buffer in the selected PHY device is full or almost full, even if a packet has not been completely transmitted.
In the receive direction, the UTOPIA packet interface defines an “Available Signal” which similar to RxClav in the standard UTOPIA interface to indicate whether the PHY layer device has a certain length data (a Chunk whose size can be 16, 48, 64 bytes etc.) ready to transmit. The UTOPIA packet interface provides a control handshaking to indicate that the data and related control signals are valid or not to guarantee the integrity of a packet.
Prior art FIG. 3 illustrates the POS-PHY UTOPIA packet interface supporting Multiple PHY(MPHY) with Multiplexed Status Polling operation. As shown in FIG. 3, in the transmit direction, TFCLK is the same as TxClk and is used to clock transmit control signals and data. TDAT[15:0] is a 16-bit Transmit Data Bus which is the same as TxData. TENB is Transmit Enable and is the same as TxEnb. PTPA is the same as TxClav and is used to indicate that the PHY layer device is ready to receive a certain size data (a Chunk) from the LINK layer device. TADR[4:0] is the same as TxAddr and is the UTOPIA address used to poll and select the appropriate PHY device. The definition of the signals TFCLK, TDAT, TENB, PTPA and TADR follows the UTOPIA standard. In addition, POS-PHY adds some new signals to support packet transmission. These signals are: TSOP indicating Start Of Packet, TEOP indicating End Of Packet, TERR indicating packet transmit error, and STPA monitoring the buffer status of the selected PHY and allowing the LINK layer device to stop transmit data once the buffer in selected PHY device is full.
To transmit a packet, the LINK layer device polls the PTPA(TxClav) status of a PHY layer device by placing a specified address on the TADR(TxAddr) bus for one clock cycle. The PHY layer device associated with the address on the TADR bus drives PTPA high (or low) during the following cycle during which the LINK layer device places a null address on the address bus. The LINK layer device checks PTPA at a certain time after it issues TADR. Based on polled PTPA information, the LINK layer device selects a PHY device and transfers data to this PHY device by driving TENB. The LINK layer device always monitors the STPA signal and stops data transmission once STPA is deasserted. The LINK layer device drives TSOP to indicate the Start of Packet and drives TEOP to indicate End of Packet. The LINK layer device also drives TERR to indicate if transmitted packet is correct or not.
Similarly, in the receive direction, RFCLK is the receive Clock used to clock receive control signals and data. RDAT[15:0]is the 16-bit Receive Data Bus. RENB is the Receive Enable signal. PRPA indicates that a certain length data (a chunk) is available to be transmitted. RADR[4:0] is the UTOPIA address used to poll and select the appropriate MPHY device. The definition of the signals RFCLK, RDAT, RENB, PRPA and RADR follows the UTOPIA standard. In addition, POS-PHY adds some new signals to support packet transmission. These signals are: RSOP indicating Start Of Packet, REOP indicating End Of Packet, RERR indicating packet receive error and RVAL indicating the validity of data and control signals on the data bus and the control bus.
To receive a packet, the LINK layer device polls the PRPA(RxClav) status of a PHY layer device by placing a specified address on the RADR(RxAddr) bus for one clock cycle. The PHY layer device associated with the address on the RADR bus drives PRPA high (or low) during the next clock cycle while the LINK layer device puts the null address on the address bus. The LINK layer device checks PRPA at a certain time after it issues RADR. Based on polled PRPA information, the LINK layer device selects a PHY device and receives data from this PHY device by driving RENB. The LINK layer device always monitors the RVAL signal to determine if the received data is valid.
The same timing requirement must be met for the Multiplexed Status Polling operation of the UTOPIA packet interface as for the standard ATM UTOPIA interface. Prior art FIG. 4 depicts the timing requirement for POS-PHY level 2 address polling. The LINK layer device starts driving UTOPIA address N at time t1. The PHY device responds to address polling by driving Clav signal (PTPA/PRPA) high (or low) at time t2. Clav (PTPA/PRPA) becomes valid for the LINK layer device at time t3. The LINK layer device checks the Clav signal at time t4. To guarantee correct operation, the Clav signal must be valid before it is checked by the LINK layer device, i.e. at some time t3<t4.
Thus, the UTOPIA packet interface illustrates the same shortcomings as the UTOPIA ATM interface with regard to the allowable distance between the PHY device and the LINK layer device.